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ASIC/RTL Design Engineer - Senior (US)
Posted: 03/03/2026
Job Number: 27703775
Job Description
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Lead micro-architecture definition and own end-to-end RTL design of SOC blocks, ensuring targets for functionality, timing, area, and power are met.
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Develop and implement high-quality RTL in Verilog/SystemVerilog, including integration of ASIC IP into complex SOC environments.
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Perform synthesis, static timing analysis (STA), timing optimization, and ensure clean Lint/CDC/RDC signoff.
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Collaborate cross-functionally with architecture, verification, and physical design teams to drive successful tape-out.
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Implement logic for testability, debug, and support silicon bring-up and post-silicon validation of owned features.
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Develop automation and scripting solutions to improve design efficiency and contribute to clear technical documentation and design reviews.
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