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STA/SDC Engineer

San Jose, CA

Posted: 06/24/2025 Job Number: 25770590

Job Description

Job Title: STA/SDC Engineer
Duration: 12+ Months
Location:  San Jose, CA
Technical:
  • Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
  • Option to also do block level RTL design or block or top-level IP integration.
  • Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
  • Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
  • Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
  • Creating fullchip clocking diagrams and related documentation.
Minimum Qualifications:
  • Bachelor’s Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
  • Experience with block/full chip SDC development in functional and test modes.
  • Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
  • Understanding of related digital design concepts (eg. clocking and async boundaries)
  • Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming
Preferred Qualifications:
  • Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
  • Experience with Spyglass CDC and glitch analysis
  • Experience using Formal Verification: Synopsys Formality and Cadence LEC.

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Ganesh Iyer

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