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Senior ASIC Engineer, Static Timing Analysis
Posted: 04/28/2025
Job Number: 25373357
Job Description
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Develop and validate complex multi-mode/multi-corner timing constraints (SDC) for RTL and signoff
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Perform pre-route timing checks and QoR cleanup to ensure smooth STA handoff
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Debug and resolve timing violations using Synopsys Primetime/Design Compiler
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Automate flows using Tcl scripting to improve efficiency in constraint validation
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Analyze and fix RTL quality issues (Lint/CDC) early in design phase
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Execute timing regression and track progress for multimillion-gate ASIC designs
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